· Responsible for Full-chip Physical Verification Sign-off in the area of
(DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
· Co-work with Place & Route team to resolve full-chip layout integration issues.
· Coordinates with internal IP owners on IP related issues.
· Coordinates with Manufacturing Team on DRC related issues.
· Provide automation solutions to improve efficiency in tape-out flow.
· Report on tapeout issues.
· Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD
deck for various processes
· Develop layout implementation flow and physical verification flow
· Co-work with QA team to reduce the PDKs/Rule deck defects
· Implement automation scripts in C-shell and Perl
Requirements:
· Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
· Familiar with IC Design front-to-backend flow
· Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
· Proficient in script programming, such as, Tcl, Perl or C-shell
· Proficient in UNIX (Linux) platforms
· Strong communication skills, problem solving and analytical skills
Salary:
$3000-$3800 for 0-3 working experience
$3800-$5500 for 3-5 working experience
$5500-$6500 for 5-8 working experience
Please contact me （123456艾特 一六三 点 com） if interested in this career development opportunity
